Technical Field
The present disclosure relates to methods and devices for enhancing mobility of charge carriers. Some embodiments of the present disclosure relate particularly to integrated circuits with metal-gate semiconductor devices, in which the channel of one type of metal-gate semiconductor device is compressively strained, and the channel of another type of metal-gate semiconductor device is tensiley strained.
Discussion of the Related Art
Straining the channel of a semiconductor device may improve the device's performance. Some semiconductor devices, such as transistors, have a channel through which charge carriers move when the semiconductor device is activated. The mobility of charge carriers in the device's channel may be an important factor in determining the device's performance. For example, the switching speed and/or drive strength of a semiconductor device may depend on the mobility of charge carriers in the device's channel. Straining the channel of a semiconductor device may enhance the mobility of charge carriers in the channel (relative to the mobility of charge carriers in an unstrained channel), thereby improving the device's performance (e.g., switching speed or drive strength). For example, the mobility of holes (charge carriers for some types of semiconductor devices, such as n-channel MOSFETs) may be enhanced in a tensiley strained channel. A tensiley strained channel may be deformed (e.g., stretched) by the application of a tensile stress. As another example, the mobility of electrons (charge carriers for some types of semiconductor devices, such as p-channel MOSFETs) may be enhanced in a compressively strained channel. A compressively strained channel may be deformed (e.g., compressed) by the application of compressive stress.
Techniques for fabricating semiconductor devices with strained channels are known. Strain may be induced in a silicon substrate by growing the silicon substrate on top of another crystalline substrate with a different lattice. For example, tensile strain may be induced by growing a silicon substrate on top of silicon-germanium (SiGe), which has a larger lattice than silicon and therefore applies tensile stress to the silicon lattice. As another example, compressive strain may be induced by growing a silicon substrate on top of a silicon carbide (e.g., SiCP), which has a smaller lattice than silicon and therefore applies compressive stress to the silicon lattice. However, with this technique, it may be difficult to induce compressive strain in some portions of the silicon (e.g., for PFET channels) and to induce tensile strain in other portions of the silicon (e.g., for NFET channels).
A strained channel may be formed by implanting materials into a silicon substrate to change the lattice in regions of the substrate (e.g., in channel regions). For example, implantation may be used to form a tensiley strained silicon carbide (e.g., SiCP) channel region, because the larger lattice of the silicon substrate applies tensile stress to the smaller lattice of the silicon carbide channel. As another example, implantation may be used to form a compressively strained silicon-germanium (e.g., SiGe) channel region, because the smaller lattice of the silicon substrate applies compressive stress to the larger lattice of the silicon-germanium channel. However, this technique may require very low temperatures during the fabrication process (e.g., −60 C), and may exacerbate short-channel effects (SCE).
A strained channel may also be formed by forming “liners” or “capping layers” on the gates of semiconductor devices. For example, a silicon nitride liner formed on the gate of a PFET may apply compressive stress to the PFET's channel, and a different silicon nitride liner formed on the gate of an NFET may apply tensile stress to the NFET's channel. However, this technique may require additional process steps, including chemical-mechanical polishing (CMP).
When the gate of a semiconductor device includes a metallic material, the device's “metal gate” may apply stress to the channel, thereby forming a strained channel. Some metal gates may include a metallic portion and a work-function layer. The work-function layer may modulate the gate's work function, thereby giving a process engineer control over the device's band gap, threshold voltage, etc.